FPGA research

Description

Our group has a consolidated experience on the design of circuits on Field Programmable Gate Arrays (FPGAs). The main mission of our research is to develop EDA tools for exploiting re-configurable platforms such as CPLDs, Flash-based FPGAs and SRAM-based FPGAs to build designs that are resilient against the effects induced by natural or human-made radiation sources. Our target applications range from space-borne systems, to avionics systems, to ground-based systems.

 

Our EDA tools are:

 

STAR: STatic AnalyzeR inspects a design intended for being deployed on SRAM-based FPGAs and verifies if all the design rules needed to guarantee immunity against soft errors affecting its configuration memory are fulfilled. The tool now supports all the Xilinx’s devices ranging from Spartan 2 to Virtex 4, and it is compatible with Xilinx’s X-TMR.

 

DEAR: Dynamic dEpendability AnalizeR evaluates the sensitivity of SRAM-based FPGA designs against single or multiple soft errors though radiation testing and fault injection. The tool is suitable for assessing the effects of soft errors in the configuration memory of the FPGA hosting the user circuit, the user circuit’s memory elements, and the firm IP cores the FPGA may embed (e.g., processor cores) when a user-provided testbench is executed. The tool now supports all the Xilinx’s devices ranging from Spartan 2 to Virtex 4.

 

RoRA: Reliability-oriented Routing Algorithm performs the place and route of a design intended for being deployed on SRAM-based FPGAs in such a way that any soft error affecting its memory is unable to corrupt the mitigation techniques the designers adopted. The tool now supports all the Xilinx’s devices ranging from Spartan 2 to Virtex 4, and it is also compatible with Xilinx’s X-TMR.

 

HAWATi: HArdware softWAre infrasTructure inserter automates the insertion of redundancy in the software the system embeds, as well as the insertion of light-weight watchdog modules (LWWM) to track the correct execution of the redundant software. The tool now supports all the Xilinx’s devices ranging from Spartan 2 to Virtex 4, and it is also compatible with Xilinx’s X-TMR.

 

 

The design flow we propose for exploiting our EDA tools is shown in the following picture.

 

 

Our tools are the result of several collaborations with experts from the European SEE Consortium and major companies/agencies (Boeing Satellite Systems, European Space Agency, Xilinx, Actel, Atmel).

Papers

Papers on FPGA

Researchers

Matteo Sonza Reorda

 

<matteo . sonzareorda @ polito . it>

 

Luca Sterpone

 

<luca . sterpone@ polito . it>

 

Massimo Violante

 

<massimo.violante @ polito . it>

[@polito.it is omitted to prevent SPAM]

 

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